Overview

OverviewFunctional Verification is one of the most time-consuming processes in ASIC design cycle; yet a structured introductory course/training/education on this topic is often missing. Neither the educational institutes offer this nor there are vendors offering such training. While several language specific courses are offered by EDA vendors, a comprehensive training on fundamentals of functional verification is lacking. This course gives you an in-depth introduction to the different aspects of functional verification including different testbench architectures. This course covers all aspects of functional verification ranging from verification architecture to building testbenches, gate level simulation and various technologies used in verification such as simulation, formal, emulation.ObjectivesTo explore what is verification and why it is needed and how it is achieved.To examine the different testbench architectures availableTo suggest widely used guidelines and need for a methodologyTo elaborate on all the different terminologies, buzz words used in the industryTo introduce different stages in functional verification such as RTL simulation, gate level simulation, emulation etc. and to address the challenges in each one of themTable of ContentsSession 1: IntroductionASIC Design FlowParadigm ShiftVerification ChallengeA quick Verification 101Session 2: Different Verification TechnologiesSimulation basedFormal methodsEquivalence checkingModel checkingTheorem ProvingHybridEmulationFPGA basedProcessor basedSession 3: Metric Driven Verification (MDV)Code CoverageAssertion coverage (Control Centric)Functional Coverage (Data centric)Session 4: Writing TestbenchesWhat is a testbench anyway?Basic testbenchesRudimentaryTCL basedHDL based - basic onesSession 5: Coverage measurement in VerificationWhat is coverage?Types of coverageLine CoverageCondition CoverageToggle CoverageFSM CoverageFunctional CoverageSession 6: Gate Level Simulation (GLS) & SDF annotationWhat is Gate Level SimulationSDF Annotation - typical timing violationsSession 7: Regressions - keeping the design stableNeed for regressionsVerification managementSession 8: Tips & tricks, Best Known Methods (BKMs)Coding tipsMethodology notesSummary

Skills

Reviews