VLSI CAD Part II: Layout

Go to Course: https://www.coursera.org/learn/vlsi-cad-layout

Introduction

**Course Review: VLSI CAD Part II: Layout on Coursera** **Course Overview:** For those venturing into the intricate world of Very Large Scale Integration (VLSI) design, Coursera offers a comprehensive course titled "VLSI CAD Part II: Layout." This course is specifically designed for learners who have completed the prerequisite "VLSI CAD Part I: Logic" course. It delves deep into the complex processes involved in designing modern VLSI chips, which integrate billions of transistors and millions of logic gates for computation, control, and various functionalities. In this course, participants explore essential concepts and tools related to the layout phase of Application Specific Integrated Circuit (ASIC) design. With the aid of computer-aided design (CAD) tools, students learn how to navigate the challenges associated with chip design. **Syllabus Overview:** 1. **Orientation:** The course kicks off with an introductory module that familiarizes students with the learning environment and technical skills necessary for effective participation. This foundation is crucial for grasping the course's content as it unfolds. 2. **ASIC Placement:** Here, learners are introduced to the fundamentals of ASIC layout processes, covering topics such as technology libraries and the intricacies of placement and routing. The lectures emphasize the placement process, guiding students through iterative methods and mathematical optimization techniques that enable them to efficiently position millions of gates on a chip. 3. **Technology Mapping:** Building on the knowledge from placement, this module discusses the critical step of technology mapping—translating synthesized outputs into actual logic gates compatible with the technology library. The course introduces elegant algorithms involving recursive tree covering, bridging practical computer science methods with VLSI CAD. 4. **ASIC Routing:** With placement established, the course shifts to routing—connecting the myriad of gates on a chip. The focus here is on Maze Routing, a classical yet powerful technique, which serves as a foundation for adding more sophisticated functionalities. An optional programming assignment allows students to practice routing real industrial benchmarks. 5. **Timing Analysis:** After placement and routing, understanding the speed and efficiency becomes paramount. This module teaches fundamental timing models, exploring delays through logic gates and routed networks. Students engage with concepts like Arrival Times (ATs), Required Arrival Times (RATs), and Static Timing Analysis (STA)—a crucial final step in ASIC design that ensures a design meets clock timing requirements. 6. **Final Exam:** The course culminates in a final exam, allowing students to demonstrate their mastery of the content learned throughout the course. This segment encourages students to consolidate their understanding through problem sets and practical applications discussed in the preceding modules. **Recommendations:** "VLSI CAD Part II: Layout" is an indispensable course for anyone serious about a career in VLSI design and engineering. The course is well-structured and offers a deep dive into the crucial elements of chip layout, from placement to routing and timing analysis. The blend of theoretical knowledge and practical assignments is particularly beneficial for developing real-world skills. I highly recommend this course to those who have completed Part I and are eager to advance their knowledge in VLSI. It's ideal for students pursuing electrical engineering, computer engineering, and related fields. Furthermore, the practical applications and programming assignments provide hands-on experience that is often lacking in traditional classroom settings. While the course assumes prior knowledge from the first part, those committed to learning will find the content approachable and rewarding. Completing this course will undoubtedly enhance your understanding and capabilities in VLSI design—an area of significant demand in today's tech-driven landscape. Enroll now on Coursera and take a significant step toward mastering the complexities of VLSI CAD!

Syllabus

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks.

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD.

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment.

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.

There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.